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1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. 128kx32 eeprom module, smd 5962-94585 top view block diagram i/o 8 i/o 9 i/o 10 a 13 a 14 a 15 a 16 nc i/o 0 i/o 1 i/o 2 we 2 # cs 2 # gnd i/o 11 a 10 a 11 a 12 v cc cs 1 # nc i/o 3 i/o 15 i/o 14 i/o 13 i/o 12 oe# nc we 1 # i/o 7 i/o 6 i/o 5 i/o 4 i/o 24 i/o 25 i/o 26 a 6 a 7 nc a 8 a 9 i/o 16 i/o 17 i/o 18 v cc cs 4 # we 4 # i/o 27 a 3 a 4 a 5 we 3 # cs 3 # gnd i/o 19 i/o 31 i/o 30 i/o 29 i/o 28 a 0 a 1 a 2 i/o 23 i/o 22 i/o 21 i/o 20 11 22 33 44 55 66 1 12 23 34 45 56 128k x 8 8 i/o 0-7 we 1 # cs 1 #we 2 # cs 2 #we 3 # cs 3 #we 4 # cs 4 # 128k x 8 8 i/o 8-15 128k x 8 8 i/o 16-23 128k x 8 8 i/o 24-31 a 0-16 oe# features ? access times of 125, 140, 150, 200, 250, 300ns ? packaging: ? 66-pin, pga type, 27.3mm (1.075") square, hermetic ceramic hip (package 400) ? 68 lead, 22.4mm sq. cqfp (g2t), 4.57mm (0.180") high, (package 509) ? organized as 128kx32; user con gurable as 256kx16 or 512kx8 ? write endurance 10,000 cycles ? data retention ten years minimum (at +25c) ? commercial, industrial and military temperature ranges ? low power cmos ? automatic page write operation ? page write cycle time: 10ms max ? data polling for end of write detection ? hardware and software data protection ? ttl compatible inputs and outputs ? 5 volt power supply ? built-in decoupling caps and multiple ground pins for low noise operation ? weight we128k32-xg2tx - 8 grams typical we128k32-xh1x - 13 grams typical *this product is subject to change without notice. figure 1 ? pin configuration for we128k32n-xh1x pin description i/o0-31 data input/output a0-16 address inputs we1-4# write enable cs1-4# chip selects oe# output enable v cc power supply gnd ground nc not connected
2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc a 11 a 12 a 13 a 14 a 15 a 16 cs 1 # oe# cs 2 # nc we 2 # we 3 # we 4 # nc nc nc i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 gnd i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 nc a 0 a 1 a 2 a 3 a 4 a 5 cs 3 # gnd cs 4 # we 1 # a 6 a 7 a 8 a 9 a 10 v cc figure 3 ? pin configuration for we128k32-xg2tx block diagram 128k x 8 8 i/o 0-7 we 1 # cs 1 #we 2 # cs 2 #we 3 # cs 3 #we 4 # cs 4 # 128k x 8 8 i/o 8-15 128k x 8 8 i/o 16-23 128k x 8 8 i/o 24-31 a 0-16 oe# top view the wedc 68 lead cqfp lls the same t and function as the jedec 68 lead cqfj or 68 plcc. but it has the tce and lead inspection advantage of the cqfp form. pin description i/o0-31 data input/output a0-16 address inputs we1-4# write enable cs1-4# chip selects oe# output enable v cc power supply gnd ground nc not connected
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. figure 3 ac test circuit dc characteristics v cc = 5.0v, gnd = 0v, -55c t a +125c parameter symbol conditions min max unit input leakage current i li v cc = 5.5, v in = gnd to v cc 10 a output leakage current i lox32 cs# = v ih , oe# = v ih , v out = gnd to v cc 10 a operating supply current (x32) i ccx32 cs# = v il , oe# = v ih , f = 5mhz 250 ma standby current i sb cs# = v ih , oe# = v ih , f = 5mhz 2.5 ma output low voltage v ol i ol = 2.1ma, v cc = 4.5v 0.45 v output high voltage v oh i oh = -400 a, v cc = 4.5v 2.4 v note: dc test conditions: v ih = v cc -0.3v, v il = 0.3v truth table cs# oe# we# mode data i/o h x x standby high z l l h read data out l h l write data in x h x out disable high z/data out x x h write x l x inhibit capacitance t a = +25c parameter symbol conditions max unit oe# capacitance c oe v in = 0 v, f = 1.0 mhz 50 pf we1-4# capacitance hip (pga) c we v in = 0 v, f = 1.0 mhz 20 pf cqfp g2t 20 cs1-4# capacitance c cs v in = 0 v, f = 1.0 mhz 20 pf data i/o capacitance c i/o v i/o = 0 v, f = 1.0 mhz 20 pf address input capacitance c ad v in = 0 v, f = 1.0 mhz 50 pf this parameter is guaranteed by design but not tested. absolute maximum ratings parameter symbol unit operating temperature t a -55 to +125 c storage temperature t stg -65 to +150 c signal voltage relative to gnd v g -0.6 to + 6.25 v voltage on oe# and a9 -0.6 to +13.5 v note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.0 v cc + 0.3 v input low voltage v il -0.5 +0.8 v operating temp. (mil.) t a -55 +125 c operating temp. (ind.) t a -40 +85 c ac test conditions parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z0 = 75 . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. current source i oh i ol current source v z ~ 1.5v bipolar supply ~ d.u.t c eff = 50 pf
4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. write a write cycle is initiated when oe# is high and a low pulse is on we# or cs# with cs# or we# low. the address is latched on the falling edge of cs# or we# whichever occurs last. the data is latched by the rising edge of cs# or we#, whichever occurs rst. a byte write operation will automatically continue to completion. write cycle timing figures 5 and 6 show the write cycle timing relationships. a write cycle begins with address application, write enable and chip select. chip select is accomplished by placing the cs# line low. write enable consists of setting the we# line low. the write cycle begins when the last of either cs# or we# goes low. the we# line transition from high to low also initiates an internal 150 sec delay timer to permit page mode operation. each subsequent we# transition from high to low that occurs before the completion of the 150 sec time out will restart the timer from zero. the operation of the timer is the same as a retriggerable one-shot. ac write characteristics v cc = 5.0v, gnd = 0v, -55c t a +125c write cycle parameter symbol min max unit write cycle time, typ = 6ms t wc 10 ms address set-up time t as 0ns write pulse width (we# or cs#) t wp 100 ns chip select set-up time t cs 0ns address hold time t ah 100 ns data hold time t dh 10 ns chip select hold time t csh 0ns data set-up time t ds 50 ns output enable set-up time t oes 0ns output enable hold time t oeh 0ns write pulse width high t wph 50 ns
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. t address cs 1-4 # we 1-4 # data in dh t wph t wp t csh t oeh t ah t oes t as t cs oe# t wc t ds t address we 1 - 4# cs 1 - 4# data in dh t wph t wp t csh t oeh t ah t oes t as t cs oe# t ds t wc figure 5 ? write waveforms we# controlled figure 6 ? write waveforms cs# controlled
6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. read the we128k32-xxx stores data at the memory location determined by the address pins. when cs# and oe# are low and we# is high, this data is present on the outputs. when cs# and oe# are high, the outputs are in a high impedance state. this two line control prevents bus contention. notes: oe# may be delayed up to t acs - t oe after the falling edge of cs# without impact on t oe or by t acc - t oe after an address change without impact on t acc . ac read characteristics v cc = 5.0v, gnd = 0v, -55c t a +125c* read cycle parameter symbol -125 -140 -150 -200 -250 -300 unit min max min max min max min max min max min max read cycle time t rc 125 140 150 200 250 300 ns address access time t acc 125 140 150 200 250 300 ns chip select access time t acs 125 140 150 200 250 300 ns output hold from add. change, oe# or cs# t oh 000000 ns output enable to output valid t oe 0 50 0 55 0 55 0 55 0 85 0 85 ns chip select or oe# to high z output t df 60 70 70 70 70 70 ns figure 7 ? read waveforms t address cs# oe# output oh t df t acc t rc t oe t acs output valid address valid high z
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. data polling the we128k32-xxx offers a data polling feature which allows a faster method of writing to the device. figure 8 shows the timing diagram for this function. during a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on d7 (for each chip.) once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the write cycle. figure 8 ? data polling waveforms data polling characteristics (v cc = 5.0v, v ss = 0v, t a = -55c to +125c) parameter symbol min max unit data hold time tdh 10 ns oe# hold time toeh 10 ns oe# to output valid toe 55 ns write recovery time twr 0 ns we 1-4 # t oeh t dh t oe t wr high z cs 1-4 # oe # i/o 7 address toggle bit: in addition to data# polling another method for determining the end of a write cycle is provided. during the write operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the write has completed, i/o6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. note: 1. toggling either oe# or cs# or both oe# and cs# will operate toggle bit. 2. beginning and ending state of i/o6 will vary 3. any address location may be used but the address should not vary. toggle but characteristics (1) symbol parameter min max units t dh data hold time 10 ns t oeh oe# hold time 10 ns t oe oe# to output delay ns t oehp oe# high pulse 150 ns twr write recovery time 0 ns t wr high z t dh t oe t oeh we# cs# oe# i/o6 (2)
8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. page write operation the we128k32-xxx has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. successive bytes may be loaded in the same manner after the rst data byte has been loaded. an internal timer begins a time out operation at each write cycle. if another write cycle is completed within 150 s or less, a new time out period begins. each write cycle restarts the delay period. the write cycles can be continued as long as the interval is less than the time out period. the usual procedure is to increment the least signi cant address lines from a0 through a6 at each write cycle. in this manner a page of up to 128 bytes can be loaded in to the eeprom in a burst mode before beginning the relatively long interval programming cycle. after the 150 s time out is completed, the eeprom begins an internal write cycle. during this cycle the entire page of bytes will be written at the same time. the internal programming cycle is the same regardless of the number of bytes accessed. figure 9 ? page mode write waveforms page write characteristics (v cc = 5.0v, v ss = 0v, t a = -55c to +125c) page mode write characteristics symbol unit parameter min max write cycle time, typ = 6ms t wc 10 ms address set-up time t as 0ns address hold time (1) t ah 100 ns data set-up time t ds 50 ns data hold time t dh 10 ns write pulse width t wp 100 ns byte load cycle time t blc 150 s write pulse width high t wph 50 ns 1. page address must remain valid for duration of write cycle. oe# cs# we# address data
9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. figure 10 ? software block data protection enable algorithm (1) notes: 1. data format: d7 - d0 (hex); address format: a 16 - a 0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data to be loaded. writes enabled (2) enter data protect state load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address
10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. hardware data protection these features protect against inadvertent writes to the we128k32-xxx. these are included to improve reliability during normal operation: a) v cc power on delay as v cc climbs past 3.8v typical the device will wait 5msec typical before allowing write cycles. b) v cc sense while below 3.8v typical write cycles are inhibited. c) write inhibiting holding oe# low and either cs# or we# high inhibits write cycles. d) noise lter pulses of <8ns (typ) on we# or cs# will not initiate a write cycle. software data protection a software write protection feature may be enabled or disabled by the user. when shipped by white microelectronics, the we-128k32-xxx has the feature disabled. write access to the device is unrestricted. to enable software write protection, the user writes three access code bytes to three special internal locations. once write protection has been enabled, each write to the eeprom must use the same three byte write sequence to permit writing. after setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. no data will be written to the device, however, for the duration of t wc . the write protection feature can be disabled by a six byte write sequence of speci c data to speci c locations. power transitions will not reset the software write protection. each 128k byte block of the eeprom has independent write protection. one or more blocks may be enabled and the rest disabled in any combination. the software write protection guards against inadvertent writes during power transitions, or unauthorized modi cation using a prom programmer. notes: 1. data format: d7 - d0 (hex); address format: a16 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 load data xx to any address (4) load last byte to last address figure 10 ? software block data protection disable algorithm (1) exit data protect state (3)
11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. package 400: 66 pin, pga type, ceramic hex-in-line package, hip (h1) 4.60 (0.181) max all linear dimensions are millimeters and parenthetically in inches
12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. package 509: 68 lead, ceramic quad flat pack, cqfp (g2t) all linear dimensions are millimeters and parenthetically in inches
13 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. i/o 8 i/o 9 i/o 10 a 14 a 16 a 11 a 0 nc i/o 0 i/o 1 i/o 2 we 2 # cs 2 # gnd i/o 11 a 10 a 9 a 15 v cc cs 1 # nc i/o 3 i/o 15 i/o 14 i/o 13 i/o 12 oe# nc we 1 # i/o 7 i/o 6 i/o 5 i/o 4 i/o 24 i/o 25 i/o 26 a 7 a 12 nc a 13 a 8 i/o 16 i/o 17 i/o 18 v cc cs 4 # we 4 # i/o 27 a 4 a 5 a 5 we 3 # cs 3 # gnd i/o 19 i/o 31 i/o 30 i/o 29 i/o 28 a 1 a 2 a 3 i/o 23 i/o 22 i/o 21 i/o 20 11 22 33 44 55 66 1 12 23 34 45 56 lead finish: blank = gold plated leads a = solder dip leads device grade: q = compliant m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package type: h1 = 1.075" sq. ceramic hex in-line package, hip (package 400*) g2t = 22.4mm ceramic quad flat pack, low pro le cqfp (package 509) access time (ns)* improvement mark n = no connect at pins 8, 21, 28, and 39 in hip for upgrade p = alternate pin con guration for hip package organization 128k x 32 user con gurable as 256k x 16 or 512k x 8 eeprom white electronic designs corp. ordering information w e 128k32 x - xxx x x x pin description i/o0-31 data inputs/outputs a0-16 address inputs we1-4# write enables cs1-4# chip selects oe# output enable v cc power supply gnd ground nc not connected figure 12 ? alternate pin configuration for we128k32np-xh1x block diagram 128k x 8 8 i/o 0-7 we 1 # cs 1 #we 2 # cs 2 #we 3 # cs 3 #we 4 # cs 4 # 128k x 8 8 i/o 8-15 128k x 8 8 i/o 16-23 128k x 8 8 i/o 24-31 a 0-16 oe# top view * 120 available in commercial and industrial temperature only.
14 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs we128k32-xxx march 2008 rev. 12 white electronic designs corp. reserves the right to change products or speci cations without notice. device type speed package smd no. 128k x 32 eeprom module 300ns 66 pin hip (h1) 5962-94585 01h5x 128k x 32 eeprom module 250ns 66 pin hip (h1) 5962-94585 02h5x 128k x 32 eeprom module 200ns 66 pin hip (h1) 5962-94585 03h5x 128k x 32 eeprom module 150ns 66 pin hip (h1) 5962-94585 04h5x 128k x 32 eeprom module 140ns 66 pin hip (h1) 5962-94585 05h5x 128k x 32 eeprom module 300ns 66 pin hip (h1, p type pinout) 5962-94585 01h6x 128k x 32 eeprom module 250ns 66 pin hip (h1, p type pinout) 5962-94585 02h6x 128k x 32 eeprom module 200ns 66 pin hip (h1, p type pinout) 5962-94585 03h6x 128k x 32 eeprom module 150ns 66 pin hip (h1, p type pinout) 5962-94585 04h6x 128k x 32 eeprom module 140ns 66 pin hip (h1, p type pinout) 5962-94585 05h6x 128k x 32 eeprom module 300ns 68 lead cqfp/j (g2t) 5962-94585 01hmx 128k x 32 eeprom module 250ns 68 lead cqfp/j (g2t) 5962-94585 02hmx 128k x 32 eeprom module 200ns 68 lead cqfp/j (g2t) 5962-94585 03hmx 128k x 32 eeprom module 150ns 68 lead cqfp/j (g2t) 5962-94585 04hmx 128k x 32 eeprom module 140ns 68 lead cqfp/j (g2t) 5962-94585 05hmx

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